1. Introduction

The push to build bigger, better, and faster computers has accelerated in recent times thanks to the advent of technologies like Big Data and Machine learning. In high-performance computing (HPC) the push to exascale performance (i.e. building a computer with 1018 floating-point operations per second) has put a strain on existing technologies. Systems with up to 100,000 sockets are now being built as the avenues to improve socket performance are being limited by other factors. To achieve such scales HPC systems will require affordable interconnects. Photonics networks are already widely deployed because they provide the bandwidth and reach that is required to build modern HPC systems. However, in its current implementation HPC photonics relies on expensive active optical cables (AOCs) and therefore its reach is limited by overall system cost considerations. In addition to lowering the system costs, low-cost photonic links can enable new, high-performance architectures. Silicon photonics (SiPh) is considered one of the most promising technologies to enable low-cost optical links. In the past few years, SiPh has demonstrated a significant market penetration in datacenters and HPC. This penetration has been driven by companies that deployed a vertically integrated business model whereas they exclusively own much of the intellectual property involved in the design and assembly of SiPh components. The current business model for SiPh is different to the foundry and OSAT (outsourced assembly and test) model that has been common in the semiconductor industry. With its steep entrance barrier, the vertical model stifles innovation and tends to favor established players in the space. Leveraging over a decade of research expertise  in SiPh (both CMOS compatible and heterogeneous III-V-on-Si platforms), we are aiming to develop a more open SiPh industrial ecosystem targeted at computer-com applications in datacenters and HPCs. The open SiPh ecosystem would make available to the design community a new way to design, build, test, and assemble SiPh PICs (Photonics Integrated Circuits) using verified IP, industry standard tools, and verified fabrication and assembly processes. Whereas initial applications target optical interconnects in datacom and HPC applications, the same platform can also be used for optical information processing.

2. CMOS Silicon Photonics

One of the key advantages of SiPh is that the fabrication process is compatible with standard CMOS processes and therefore can use the same tools and leverage years of innovation that happened to support the large volume CMOS market. For example, several foundries have developed 300- mm SiPh lines that leverage existing processes especially in the back end of the line (BEOL). More recently several foundries have started combining SiPh and through-silicon vias to build SiPh interposers. The comparison of the two packaging strategies is shown in Figure 1. Through Si via (TSV) packaging opens the way to a close 3D integration of the photonic and logic chips.

Figure 1. SiPh packaging options, wire bonded (2.5D) and TSV (3D).

2.1. Development status

Our group has been focusing on using CMOS SiPh to implement dense wavelength division multiplexing (DWDM) links. A schematic of the transmitter and receiver for high radix switch application is shown in Figure 2. Rather than bundling up several single-wavelength lasers together, a comb laser is a better choice here to generate tens of high-quality continuouswave (cw) wavelengths with inherently fixed channel spacing. This stream of multi-wavelength laser output can be split or deinterleaved to feed multiple arrays of microring resonators which provide energy-efficient data modulation and WDM function simultaneously. Modulated signals are coupled to fiber ribbon through low loss grating couplers (GCs). In the receiver side a similar array of microrings drops the signal to corresponding photodetector to finish O/E conversion. Significant reduction in the link power consumption is possible when employing highly sensitive detectors, such as avalanche photodetectors (APDs).

Figure 2. Schematic diagram of the DWDM transmitter and receiver.

We recently demonstrated a 24-channel version of the DWDM transceiver [1]. A picture of the wire bonded assembly is shown in Figure 3. The CMOS driver/receiver chip (code named Iceman) channels implemented in a 28-nm process. The SiPh interposer (code named Halla), fabricated in a 65-nm process, consists of a transmitter waveguide with two grating couplers and 24 modulator rings and a receiver waveguide with a single grating coupler and a bus waveguide with 24 silicon microring filters and 24 photodetectors (PDs). The receiver chip and SiPh interposer are flip chip packaged using state-of-the-art 3D packaging technology.

Figure 3. Picture of a silicon photonics circuit with flip-chip integrated drivers and removable connector.

The Iceman chip consists of three parts: 1) digital logic with industry-standard interface, 2) high-speed front-end circuits, and 3) wavelength monitoring and tuning circuits. The digital logic block in Iceman, which is compatible with the Peripheral Component Interconnect express (PCIe) standard, provides the data pattern to the transmitter and checks bit-error from the received data for 24 channels through the serializer and de-serializer. Inter-integrated circuit (I2C) block is also included to send and receive the control commands using an externally connected field-programmable gate-array (FPGA). The transmitter front-end circuits drive the Si p-i-n microring modulators at the data-rate of 16 Gb/s/wavelength and includes 1-tap pre-emphasis equalizer that compensates sub-GHz bandwidth of the carrier-injection to achieve the target data-rate. An on-chip AC-coupling is implemented at the transmitter to employ pseudo-differential signaling scheme so that the microring modulators are biased correctly and have sufficient modulation amplitude. The receiver front-end circuits consist of trans-impedance amplifier (TIA), automatic gain control (AGC) circuit and a linear equalizer. The TIA converts current signal from the photodetector to a voltage signal with a large gain using two feedback resistors. The linear equalizer compensates the bandwidth limit from the transmitter as well as packaging parasitics by employing source degeneration and negative capacitance techniques. The AGC circuit allows a wide input current dynamic range to accommodate potential signal fluctuation from highly sensitive microring devices. The wavelength monitoring circuit uses an analog-todigital converter with successive approximation resistor logic (SAR ADC) to capture how far the resonance wavelength of each microring is from the target wavelength by monitoring the amplitude and DC value of transmitted or received optical signal. The digitized output of the SAR-ADC controls the tuning circuits that inject current into the silicon photonic heaters located in the proximity of the microrings using a current- steering digital digital-to-analog converter (DAC). The assembly is driven by an external laser and on-chip drivers and receivers able to sustain speeds up to 16 Gbps. The aggregate bandwidth per fiber is 384 Gbps.

2.2. Tool Development

A robust set of design tools is a key ingredient for a successful SiPh ecosystem. Design tools enable technologists to access the underlying technologies easily and transparently. There are several different tools that are required for a complete ecosystem

1) Device design tools. These tools are used by device designers to optimize device performance and create the models that can be used in the design of complex circuits. In the past few years there has been an explosion of tools that allow the simulation and optimization of photonic devices. Some tools are suited for a particular type of device or analysis. Others are integrated and help streamlining the device designer workflow from device conception and layout to the initial simulation and finally to test, verification, and model build. A compact model library (CML) is the outcome of the workflow and can be widely distributed to circuit designers and used in a system simulation tool to ensure end-to-end performance.

2) System design. Design automation is one of the key requirements for the system design tools. We strive to reproduce the electronic design workflow for SiPh. This workflow starts with a schematic of the circuit, progresses to a verification stage using the compact models, and then moves to the circuit layout using an automated layout tool. Once the layout is complete a layout-versus-schematic tool verifies that the final layout reflects the original design intent. The final step before tape out is the verification that the layout complies with the process design rules. This workflow has been at least partially realized thanks to tools from several EDA companies.

3) Packaging and co-design. Soon 2.5D and 3D co-packaging of PICs and drivers will become more prevalent in the industry. This creates the need to co-simulate the thermal and power performance of the chips. Heating from power grids and through-silicon vias can affect the performance and reliability of the photonic components and these effects must be considered at the design stage. Our group has partnered with industry-leading EDA companies to develop tools in this space [2].

4) Device optimization and models. Recently, the performance of SiPh devices has progressed much thanks to the use of a variety of optimization techniques. These techniques couple electromagnetic simulation tools with optimization techniques inspired by other areas of science and engineering such as machine learning and genetic optimization algorithms. Our group has been active in the design and optimization of individual devices. For example, we have used adjoint methods [3] as an effective and powerful tool for optimizing photonic devices such as grating couplers that comprise many parameters. The adjoint method simplifies the exploration of large parameter spaces by calculating the gradients of the problem Figure-of-Merit (FoM) in an efficient manner.

3. Heterogeneous III-V-on-Si Photonic Integration

Heterogeneous III-V-on-Si integration is a novel technology with proven volume manufacturability. It marries the merits of III-V direct-bandgap materials with SiPh to overcome their respective limits of small wafer scale and integration density for PIC production and lack of efficient optical gain or other useful electro-optic properties. As shown in a cross-sectional scanning electronic microscopy (SEM) in Figure 4, ~2 mm-thick III-V epitaxial structure on the SOI substrate enables high-performance lasers, amplifiers, phase or absorption modulators and photodetectors [5]. These are great complementary building blocks to CMOS SiPh components for full PIC enablement and versatile applications.

3.1. Transceiver Architecture and Key Building Blocks

We are on the way to demonstrate a fully integrated DWDM transceiver on our heterogeneous III-V-on-Si platform. A possible implementation schematically shown in Figure 4. Like the DWDM architecture realized in the CMOS SiPh transceiver chip we use a high-performance InAs quantum-dot (QD) comb laser with optional integrated QD semiconductor optical amplifier (SOA) as the multi-wavelength source. In this architecture the laser is on chip and generates tens of evenly spaced wavelengths. One multi-wavelength stream is either split by power splitters or deinterleaved in the spectral domain into two or more streams to feed parallel compact microring modulator arrays to complete the transmitter function. On the same chip similar microring resonators are used as demultiplexer (DEMUX) to drop each channel of optical data into the corresponding high-sensitivity avalanche photodetector (APD) to complete the receiver function. Low loss grating couplers serve as I/O ports to fiber ribbons. The project is targeting 25 Gb/s/channel with 40 channels in total to reach an aggregate bandwidth of >1 Tb/s with <1.5 pJ/bit energy efficiency.

Figure 4. Schematic of a 40-channel heterogeneous DWDM transceiver chip, and experimental highlights of key building blocks as insets.

3.2. Development Status

Compared with standalone monolithic mode-locked comb lasers, our heterogeneous platform offers a critical advantage of design flexibility in channel spacing without compromising output power and a single saturable absorber for simple control [6]. By designing a compound laser cavity with low-loss Si waveguide and taking advantage of the Vernier effect between the two coupled cavities channel spacing and device length are decoupled from each other. Laser efficiency and output power can be optimized independently of channel spacing. The intrinsic properties of quantum dot materials favor robust lownoise comb line generation, as shown the spectrum in Figure 4 showing a 100 GHz-spaced flat comb spectrum with 15 useable channels [6]. A record 220 comb lines with 15.5 GHz channel spacing from a single comb laser were also demonstrated recently [7]. Our group is also working on heterogeneous SOAs and preliminary data is very encouraging.

We also developed an III-V/oxide/Si MOS capacitor (MOSCAP) (Figure 4 inset, TEM image) to provide athermal, ultra-low power consumption phase shift for deinterleaver, modulators and microring drop filters in DC condition, as well as high-speed, low-loss data modulation [8]. We observed a wavelength shift over 1 nm in a 40 μm-diameter heterogeneous microring resonator with 4 V bias on the MOSCAP. We measured ~50 fA leakage current that translates into a power consumption over 1 billion times lower than than widely used thermal tuning [9]. The same MOSCAP will also be integrated in heterogeneous comb laser to help locking the comb lines with MOSCAP microring modulators and drop filters with negligible power consumption. The MOSCAP concept has been employed in pure Si modulators, in this case, the lower effective mass and larger mobility for electrons in the III-V material, result in more effective plasma dispersion effect and other electro-optic effects in III-V will also benefit [8]. Such a MOSCAP microring modulator is illustrated in the inset of Figure 4. An eye diagram of 28 Gb/s non-return-to-zero (NRZ) without any equalization drive was measured recently [10]. The modulator has a good extinction (8 dB here) and low insertion loss (<0.5 dB here) comparable to those of carrierinjection p-i-n modulators. These properties are critical for good signal integrity and low laser/SOA power consumption in this cascaded microring-based DWDM architecture. Ongoing improvement in design and fabrication is expected to extend the current RC constant-limited bandwidth to enable >40 Gb/s modulation, and 1.6 Tb/s aggregate bandwidth from this ~mm2 chip.

On the receiver side, there are two flavors of Si-based APDs in our roadmap, viz. SiGe APDs and InAs QD APDs. Internal gain in the APD enables the detection of weak optical signal if good sensitivity can be achieved. The strong optical absorption in Ge and the small impact ionization coefficient ratio of Si (~0.02) make a separate absorption carrier multiplication (SACM) SiGe APD structure ideal for high responsivity and low excess noise [11]. Reflector-assisted designs allow further improvements of the gain without sacrificing the overall bandwidth to reach a gain-bandwidth product (GBP) of 497 GHz and 40 Gb/s NRZ and 80 Gb/s PAM4 operation [12]. A sensitivity of -13.5 dBm at 32 Gb/s NRZ operation (limited by our Bit Error Rate Tester) resulted in error-free operation with a bit error rate of 10-12. Calculations indicate an 8X reduction in total link power consumption to achieve sub-pJ/bit link energy efficiency goal when receiver sensitivity is improved to -20 dBm at 25 Gb/s. SiGe APDs also have the advantage of being CMOS-compatible in the fabrication process. However, a process integration challenge will arise when attempting to integrate the SiGe and heterogeneous III-V processes together.

For this reason, we were thrilled to discover that the InAs QD laser epitaxial material can be used as an APD as well if enough reverse bias was provided [13]. In addition to ultra-low dark current density ~ 1 nA/cm2, most recent measurement showed 20 GHz bandwidth and 585 GHz GBP, both records for QD APDs [14]. Open eye diagram at 25 Gb/s NRZ data rate reaches a dynamic goal, and sensitivity characterization is under the way. As QD APDs were fabricated on the same chip with heterogeneous comb lasers and MOSCAP modulators, there is no roadblock to accomplish full transceiver integration in near future.

Progress in all these individual building blocks endows great flexibility and confidence for us to march towards the ultimate project goal of a fully integrated 1 Tb/s DWDM transceiver chip. A proof-of-concept DWDM transmitter link with aggregated bandwidth of 200 Gb/s (8×25 Gb/s) will be reported at the OSA advanced photonics congress in July 2021 [15].

4. Optical Information Processing

In addition to reaping the benefits of having cheaper, faster, higher bandwidth and more energy-efficient SiPh-based optical interconnects inside HPC systems, our group has also explored the possibility to leverage the same scalable CMOS-compatible platform to offload certain computations from digital electronic chips to specialized photonic accelerators. In 2014 we published a theoretical study, proving that optical nonlinearities in ring resonators are sufficient to obtain a cascadable universal set of logical gates [16]. To obtain ultimate energy efficiency, optical nonlinearities can be engineered in a scalable way such that switching energies with ~10s of aJ inside the ring resonators become feasible, allowing these photonic logic system to operate at the few-photon limit. Further lowering the photon number in the cavities would result in quantum fluctuations overpowering the signal, therefore hampering the desired functionality of the logic gates.

In 2016, we theoretically proposed how optical nonlinearities causing self-phase modulation in microring resonators can be utilized to emulate coherent Ising machines in an integrated photonics platform [17,18]. Ideally, ultrafast all-optical nonlinearities such as the Kerr-effect would be utilized inside the circuits representing the Ising nodes (or neurons). However the proposed scheme is also compatible with free-carrier based nonlinearities and even the much slower thermal nonlinearities in integrated photonics material stacks where the Kerr-effect is not yet readily available. Coherent Ising machines can be utilized to solve intractable combinatorial optimization problems and have an architecture which is reminiscent of Hopfield neural networks, which is a recurrent neural network in which the neuron states need to be interpreted in a binary way. At its core, the proposed integrated coherent Ising machine uses programmable multiport Mach-Zehnder interferometer meshes to efficiently calculate a matrix-vector product to update the Ising node states until convergence (Figure 5).

Figure 5. The SiPh platform can also be used to implement photonic accelerators such as this 4-node coherent Ising machine circuit. Like many other neuromorphic-inspired photonic accelerators, at its core, the proposed Ising machine contains an optical engine for efficient matrix vector products. To be energy-efficient, the tuning mechanism for this matrix should be non-volatile.

The ability to store a matrix inside a programmable integrated photonic circuit that can efficiently perform matrix vector multiplications at low latency can also be leveraged in related photonic deep learning or neuromorphic accelerator architectures, either by taking advantage of the aforementioned MZI meshes, or by utilizing ring-based DWDM routing using similar building blocks as used in the transceiver circuits for datacom/HPC applications [19]. Importantly, to be competitive in terms of energy-efficiency and cost with emerging (analog) electronic accelerators, the SiPh platform needs to enable non volatile in-memory processing. Specifically, the tuning mechanism utilized inside the photonic circuits storing the matrices with the neural network’s synaptic weights, should be based on physics that is compatible with persistent information storage (in contrast to power consuming tuning using, e.g., heaters). Amongst several options such as phase-change materials, the ferro-electric effect, opto-mechanics, our group is currently focusing its efforts on the usage of memristive photonic devices based on the hybrid III-V-on-Si platform, as it allows for compact non-volatile multi-state tuneability using the same scalable fabrication process as the one we have described in Section 3 [20].

5. Future Upgrades

We focus here on a couple of possible future upgrades of the CMOS SiPh and heterogeneous SiPh platforms:

Grating couplers (GCs) are an appealing and scalable solution for optical I/O in large-scale integrated photonic circuits that allows for wafer-level testing. In the traditional design, coupling to a mode propagating along the direction perpendicular to the chip results in a large backreflection into the waveguide. Therefore, most applications use GCs that couple light into a mode that is slightly tilted off-axis. On-axis gratings could improve could be used to reduce the alignment tolerance in grating coupled lasers and build optical vias in multi-layer 3D photonics applications. Using new design approaches, including adjoint design method [21], our group has designed and tested vertical GCs that can be fabricated using only a single-etch step in a 193nm DUV immersion lithography process, while maintaining good coupling and low reflection. We have measured insertion losses of less than 2 dB, bandwidths larger than 20 nm, and moderate in-band reflection of less than -10 dB [21]. On the other hand, for the heterogeneous platform, a III-V thin film overlay on Si can form a novel GC structure to enable increased directionality toward the optical fiber, like previous demonstrated ones with polysilicon overlay [22]. It represents an example of fully taken advantage of wafer-bonded III-V material not only for active but also passive functionality.

A high-speed modulator based on p-n depletion mode is the latest Si modulator structure we are adding into our toolbox and PDK family in addition to p-i-n injection and MOSCAP-based ones. The first attempt has been rewarding by demonstrating a two-segment 100 Gb/s PAM4 microring modulator from a standard CMOS foundry multi-project processing run [23]. It can instantly enhance the aggregated bandwidth to 2.4 Tb/s if we implement this design in the same 24-channel DWDM CMOS SiPh transceiver without much change in process and chip footprint.

Optical power monitoring is critically necessary for integrated photonic system in debug, performance, and lifetime monitoring. We are developing novel power monitoring techniques to harvest optical power in passive and active components without the need for conventional monitor photodiodes that measure a small portion of the light, tapped from a waveguide, thereby reducing loss and complexity in layout, fabrication, and power requirements.

Finally, both for datacom as well as optical information processing applications, incorporation of ultra low-loss waveguides (<1dB/m loss) and/or having access to ultrafast optical nonlinearities such as the Kerr-effect is a worthwhile addition to the hybrid III/V-on-Si platform. For instance, in 2021, integration of InP/Si lasers with ultra low-loss SiN waveguides has resulted in a successful demonstration of single-soliton comb sources, which is a major milestone for this technology. More generally, the ability to combine the advantages of the aforementioned III/V-on-Si platform with the nonlinear and low-loss properties of SiN, potentially in a multilayer topology, brings unseen capabilities to the original SiPh platform, as it allows system-level designers to pick the optimal material layers for the desired device functionality, without the need to go off-chip.

6. Summary

We here presented a high-level overview of our vision and approach in advanced SiPh development primarily for high-performance connectivity in computer-com applications in datacenters and HPCs. We develop in parallel CMOS SiPh and heterogeneous III-V-on-Si platforms, continuing to innovate device structures, process integration, architecture, packaging, and system implementation. We are also extending our SiPh R&D domain from communication to computing, e.g., optical neuromorphic computing. The world first demonstration of a memristor laser [20] recently provides new sparks to ramp up effort in computing applications our group initiated a few years back [17,18]. More and more emerging applications in communications, metrology and sensing are further pushing the momentum to drive innovations and grow SiPh into a much larger business. Our commitment to promote and lead the development of an open ecosystem with our foundry and supply chain partners will help our work to generate larger impact not only for our business but also to the entire integrated photonics community.

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